
module param_counter_top ( count, clk, count_enable, count_reset, out_enable
 );
  output [7:0] count;
  input clk, count_enable, count_reset, out_enable;
  wire   \u_counter/N6 , \u_counter/N5 , \u_counter/clock_wire ,
         \u_counter/N0 , n2, n5, n6, n7, n8, n10, n11;
  wire   [2:0] Xfer;
  assign \u_counter/N0  = count_enable;

  TBUFX20 \u_converter01/out_bus_gate_tri[4]  ( .A(1'b0), .OE(n5), .Y(count[4]) );
  TBUFX20 \u_converter01/out_bus_gate_tri[5]  ( .A(1'b0), .OE(n7), .Y(count[5]) );
  TBUFX20 \u_converter01/out_bus_gate_tri[6]  ( .A(1'b0), .OE(n5), .Y(count[6]) );
  TBUFX20 \u_converter01/out_bus_gate_tri[7]  ( .A(1'b0), .OE(n7), .Y(count[7]) );
  TBUFX20 \u_converter01/out_bus_gate_tri[3]  ( .A(1'b0), .OE(n5), .Y(count[3]) );
  TBUFX20 \u_converter01/out_bus_gate_tri[2]  ( .A(Xfer[2]), .OE(n7), .Y(
        count[2]) );
  TBUFX20 \u_converter01/out_bus_gate_tri[1]  ( .A(Xfer[1]), .OE(n5), .Y(
        count[1]) );
  TBUFX20 \u_converter01/out_bus_gate_tri[0]  ( .A(Xfer[0]), .OE(n7), .Y(
        count[0]) );
  DFFRQX2 \u_counter/count_reg_reg[0]  ( .D(n11), .CK(\u_counter/clock_wire ), 
        .RN(n10), .Q(Xfer[0]) );
  DFFRQX1 \u_counter/count_reg_reg[2]  ( .D(\u_counter/N6 ), .CK(
        \u_counter/clock_wire ), .RN(n10), .Q(Xfer[2]) );
  DFFRQX1 \u_counter/count_reg_reg[1]  ( .D(\u_counter/N5 ), .CK(
        \u_counter/clock_wire ), .RN(n10), .Q(Xfer[1]) );
  XNOR2XL U8 ( .A(Xfer[1]), .B(n11), .Y(\u_counter/N5 ) );
  CLKINVX32 U9 ( .A(n6), .Y(n5) );
  CLKINVX32 U10 ( .A(n6), .Y(n7) );
  INVX16 U11 ( .A(n8), .Y(n6) );
  XNOR2XL U12 ( .A(Xfer[2]), .B(n2), .Y(\u_counter/N6 ) );
  INVXL U13 ( .A(Xfer[0]), .Y(n11) );
  INVX2 U14 ( .A(count_reset), .Y(n10) );
  MX2X1 U15 ( .A(1'b0), .B(clk), .S0(\u_counter/N0 ), .Y(
        \u_counter/clock_wire ) );
  NAND2XL U16 ( .A(Xfer[1]), .B(Xfer[0]), .Y(n2) );
  BUFX8 U17 ( .A(out_enable), .Y(n8) );
endmodule

